Issue
I was looking into Linux support for the RISC-V 32 Bit and came across the following compile instructions:
make ARCH=riscv CROSS_COMPILE=riscv32-unknown-linux-gnu- -j $(nproc)
The issue is that riscv32
does not make it clear if just the base CPU instruction set is needed (RV32I) or if additional extensions are needed/toggleable (RV32IMAC
seems to be a common target).
This leaves me with the following questions:
- What CPU instruction set or sets is implied in above command?
- If not RV32I, can optional arguments be added to support RV32I?
Solution
From what I can see in the Linux kernel v5.19 the Makefile
for RISC-V (arch/riscv/Makefile
) looks like this:
# ISA string setting
riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
The ISA used is rv32ima
for 32-bit RISC-V kernels. Additionally, the f
, d
and c
extensions can also be enabled by configuring CONFIG_FPU
(for fd
) and CONFIG_RISCV_ISA_C
(for c
). By default these two are both set to y
so you have rv32imafdc
, however you can disable fdc
if you run menuconfig
(or similar) and set CONFIG_FPU=n
and CONFIG_RISCV_ISA_C=n
.
Note: this is for Linux v5.19. You will have to make sure yourself by inspecting the Makefile
of your kernel if you have a different version.
can optional arguments be added to support RV32I?
No, it does not look like so, rv32ima
is the minimum set of extensions selected when tarteging RISC-V 32bit. But again, if you have a different kernel version lower than v5.19 you'd have to check your Makefile
to make sure (maybe some older kernels are fine with just rv32i
).
Answered By - Marco Bonelli Answer Checked By - Dawn Plyler (WPSolving Volunteer)